1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a metal interconnect layer of a semiconductor device and a method for forming the metal interconnect layer.
2. Description of the Related Art
For higher integration density and rapid operation of integrated circuit chips, semiconductor integration techniques have been advanced. The size of chips has been decreased with a smaller design rule to satisfy the need for high integration level. To increase the operation speed of chips, performance of transistors has been enhanced by reducing the parasitic resistance and parasitic capacitance of the transistors.
With regard to interconnection techniques for semiconductor devices, it is significant to design a high-performance transistor with a minimum resistance and parasitic capacitance, such that an RC level (resistance×capacitance) of a semiconductor device having the capacitor is low. The resistivity of copper (Cu), 1.8 μΩ-cm, is lower than that of aluminum (Al), 2.7 μΩ-cm. Due to the low resistance of Cu, there is a thickness reduction effect when a metal interconnect layer is made of Cu. For this reason, use of Cu as a material for metal interconnect has proliferated to reduce interconnection resistance and parasitic capacitance with a 0.18 μm or less design rule.
FIGS. 1 and 2 illustrate the configuration of metal interconnects formed by a conventional damascene process. For the metal interconnects shown in FIGS. 1 and 2, the conductive layers are formed of Cu. In particular, a trench is formed in an interlevel dielectric (ILD) film, and a barrier layer 16 and a conductive layer 18 are deposited in sequence, filling the trench. Then, the semiconductor wafer 10 is subjected to chemical mechanical polishing. Such processes are collectively called “damascene processes.” When a metal interconnect is formed by the conventional damascene process, a lifting of the conductive layer 18 in the trench may occur due to stress applied to the ILD film 12 during a subsequent thermal process. This problem is serious when the upper width of a trench is larger than the lower width, as shown in FIG. 2. When such lifting of a metal connection occurs in a trench, the contact between a via and the metal interconnect is unsatisfactory, so that normal operation of semiconductor chips is impossible.
FIG. 3 illustrates lifting of a metal interconnect in a trench. As the trench angle (θ) in the ILD film becomes smaller, it is more likely that lifting of the conductive layer 18 will occur.